Layer structure having contact hole, fin-shaped capacitor using the layer structure, method of producing the fin-shaped capacitor, and dynamic random access memory having the fin-shaped capacitor

ABSTRACT

A method of forming a structure having a contact hole includes the steps of (a) forming an insulating layer on a first conductive layer, (b) forming a second conductive layer on the insulating layer, (c) forming an opening in the second conductive layer, (d) forming a conductive sidewall around an inner wall of the first conductive layer defining the opening, (e) selectively etching the insulating layer in a state where the second conductive layer and the conductive sidewall function as etching masks, so that the contact hole having a width smaller than that of the opening and defined by the conductive sidewall is formed, and the first conductive layer is exposed through the contact hole, and (f) removing the second conductive layer and the conductive sidewall.

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to a layer structurehaving a contact hole suitable for dynamic random access memories havingfine contact holes, and a method of producing such a layer structure.More particularly, the present invention is concerned with a fin-shapedcapacitor having such a layer structure, and a method of forming such afin-shaped capacitor. Furthermore, the present invention is concernedwith a dynamic random access memory having such a fin-shaped capacitor.

[0002] Recently, there has been considerable activity as regards thedevelopment of 64 Mbit dynamic random access memories (DRAM). There areknown DRAMs having three-dimensional stacked capacitor cells capable ofproviding a storage capacity equal to or higher than 64 Mbits (seeJapanese Laid-Open Patent Application Nos. 1-137666, 1-147857 and1-154549, U.S. Pat. No. 4,974,040 and T. Ema et al., “3-DIMENSIONALSTACKED CAPACITOR CELL FOR 16M AND 64M DRAMS”, International ElectronDevices Meetings, 592-IEDM 88, Dec. 11-14, 1988). In order to increasethe integration density, it is necessary to reduce the two-dimensionalsize of each memory cell without reducing the capacitance of eachstacked capacitor.

[0003] In order to fabricate 64 Mbit DRAMs, a feature scaleapproximately equal to 0.3 [μm] is required. However, the conventionalphotolithography technique can realize a feature scale approximatelyequal to a maximum of 0.5 [μm]. 64 Mbit DRAMs can be realized byreducing the size of each storage (stacked) capacitor. For this purpose,it is necessary to reduce the size of a contact window (opening) for astorage electrode which is a part of the stacked capacitor. As describedabove, since the feature scale realized by the conventionalphotolithography technique is approximately 0.5 [μm], it is impossibleto form the contact window having a size approximately equal to 0.3[μm]. It is also necessary to reduce the size of a window (contact hole)provided for connecting a word line formed of, for example, polysilicon,and a low-resistance wiring line (word-line shunt layer) formed of Al orAl alloy, directed to preventing the occurrence of a delay in signaltransmission in the word line.

[0004] Japanese Laid-Open Patent Application No. 63-119239 discloses amethod for forming a fine pattern narrower than a feature scale limit ofthe conventional photolithography technique. The application teaches aprocess in which polysilicon, PSG or SiO₂ is grown on an SiO₂ maskhaving a window through which a substrate is partially exposed, and agrown film on the mask and the exposed substrate surface isanisotropically etched, so that a sidewall is formed on the substrate sothat it is formed around the entire inner wall of the window in themask. The distance between opposite surfaces of the sidewall in thewindow is less than the feature scale limit. Thus, a surface area of thesubstrate less than the feature scale limit is exposed through thesidewall in the window. Then, the substrate is etched in such a way thatthe combination of the sidewall and the mask function as an etchingmask, so that a hole is formed in the substrate.

[0005] The above-mentioned Patent Application discloses an arrangementin which the mask is formed of SiO₂ and a member to be processed isformed of Si. Thus, the removal of the mask material can be easily made.However, when a multilayer structure, such as DRAMS, is produced, it isnecessary to consider three layers of a mask material, a material to beprocessed and a underlying material which is located under the processedmaterial and which is exposed through a hole formed in the processedmaterial. In this case, it is necessary to prevent the exposed portionof the underlaying material from be damaged during a process in whichthe mask material is removed. Further, if the mask material is left inthe finalized products, it is necessary to have no problem arising fromthe existence of the left mask material. The above-mentioned JapaneseApplication does not suggest the above matters.

[0006] Japanese Laid-Open Patent Application No. 60-224218 discloses theuse of a sidewall directed to providing a window (contact hole) smallerthan the feature scale limit of the conventional photolithographytechnique. The sidewall is formed of Al and formed on an SiO₂ layer andaround an inner wall of a window formed in a silicon nitride (Si₃N₄)layer also formed on the SiO₂ layer. The SiO₂ layer is selectivelyetched in such a way that the Al sidewall and the Si₃N₄ layer functionas mask layers. However, it is very difficult to form the Al sidewall incontact with the inner wall of the window in the Si₃N₄ layer, since Alhas a poor coverage characteristic. Further, it is necessary to form theSi₃N₄ layer which is sufficiently thick, because the selective etchingratio of Si₃N₄ to SiO₂ is small.

[0007] Japanese Laid-Open Patent Application No. 63-116430 (whichcorresponds to U.S. patent application Ser. No. 924,223 filed on Oct.28, 1986) teaches the use of a sidewall for forming a hole smaller thanthe scale limit of the conventional photolithgraphy technique. The justabove application shows a lift-off process for removing the maskmaterial. However, the lift-off process has a problem in that some ofthe mask material separated from the substrate is re-adhered hereto.This frequently causes a pattern fault in a subsequent process. TheJapanese application of concern does not disclose an effective step toprocess the mask material. Further, the Japanese application shows asidewall formed on the side surface of a photosensitive material. It isnecessary to form the sidewall at a low temperature due to the thermalstability of the photosensitive material. Thus, there is a greatlimitation regarding the selection of mask materials. In addition, thestructure shown in the Japanese application of concern is limited to aspecial application.

SUMMARY OF THE INVENTION

[0008] It is a general object of the present invention to provide animproved layer structure having a contact hole, in which theabove-mentioned disadvantages are eliminated.

[0009] A more specific object of the present invention is to provide alayer structure having a contact hole suitable for DRAMs.

[0010] The above-mentioned objects of the present invention are achievedby a method of forming a structure having a contact hole comprising thesteps of:

[0011] (a) forming an insulating layer on a first conductive layer;

[0012] (b) forming a second conductive layer on the insulating layer;

[0013] (c) forming an opening in the second conductive layer;

[0014] (d) forming a conductive sidewall around an inner wall of thefirst conductive layer defining the opening;

[0015] (e) selectively etching the insulating layer in a state where thesecond conductive layer and the conductive sidewall function as etchingmasks, so that the contact hole having a width smaller than that of theopening and defined by the conductive sidewall is formed, and the firstconductive layer is exposed through the contact hole; and

[0016] (f) removing the second conductive layer and the conductivesidewall.

[0017] The above-mentioned objects of the present invention are alsoachieved by a method of forming a structure having a contact holecomprising the steps of:

[0018] (a) forming an insulating layer on a first conductive layer;

[0019] (b) forming a second conductive layer on the insulating layer;

[0020] (c) forming an opening in the second conductive layer;

[0021] (d) forming a conductive sidewall around an inner wall of thefirst conductive layer defining the opening;

[0022] (e) selectively etching the insulating layer in a state where thesecond conductive layer and the conductive sidewall function as etchingmasks, so that the contact hole having a width smaller than that of theopening and defined by the conductive sidewall is formed on theinsulating layer and the first conductive layer is exposed through thecontact hole;

[0023] (f) forming a barrier layer on the second conductive layer, theconductive sidewall and the first conductive layer exposed through thecontact hole; and

[0024] (g) forming a third conductive layer on the barrier layer, thebarrier layer preventing the third conductive layer from reacting withthe second conductive layer and the conductive sidewall.

[0025] The above-mentioned objects of the present invention are alsoachieved by a method of forming a structure having a contact holecomprising the steps of:

[0026] (a) forming an insulating layer on a first conductive layer;

[0027] (b) forming a second conductive layer on the insulating layer;

[0028] (c) forming an opening in the second conductive layer;

[0029] (d) forming a conductive sidewall around an inner wall of thefirst conductive layer defining the opening;

[0030] (e) selectively etching the insulating layer in a state where thesecond conductive layer and the conductive sidewall function as etchingmasks, so that the contact hole having a width smaller than that of theopening and defined by the conductive sidewall is formed, and the firstconductive layer is exposed through the contact hole; and

[0031] (f) forming a third conductive layer on the second conductivelayer, the conductive sidewall and the member exposed through thecontact hole,

[0032] wherein:

[0033] the second conductive layer comprises polysilicon;

[0034] the conductive sidewall comprises polysilicon; and

[0035] the third conductive layer comprises tungsten.

[0036] The aforementioned objects of the present inventoin are achievedby a method of forming a structure having a contact hole comprising thesteps of:

[0037] (a) forming an insulating layer on a first conductive layer;

[0038] (b) forming a second conductive layer on the insulating layer;

[0039] (c) forming a first opening in the second conductive layer;

[0040] (d) selectively growing a third conductive layer on the secondconductive layer and an inner wall of the second conductive layerdefining the first opening, so that a second opening defined by thethird conductive layer and having a width smaller than that of the firstopening is formed; and

[0041] (e) selectively etching the insulating layer in a state where thethird conductive layer functions as an etching mask, so that the contacthole having a width substantially identical to the second openingdefined by the third conductive layer is formed, and the firstconductive layer is exposed through the contact hole.

[0042] Another object of the present invention is to provide a layerstructure having a contact hole as formed by the above-mentionedmethods.

[0043] This object of the present invention is achieved by a layerstructure comprising:

[0044] a first conductive layer;

[0045] an insulating layer formed on the first conductive layer andhaving a contact hole, the first conductive layer being exposed throughthe contact hole;

[0046] a second conductive layer formed on the insulating layer andhaving an opening having a width larger than that of the contact hole;

[0047] a conductive sidewall formed on the insulating layer exposedthrough the opening and formed around an inner wall of the secondconductive layer defining the opening, the conductive sidewall having awidth substantially equal to that of the contact hole;

[0048] a barrier layer formed on the second conductive layer, theconductive sidewall and the first conductive layer exposed through thecontact hole; and

[0049] a third conductive layer formed on the barrier layer, the barrierlayer preventing the third conductive layer from reacting with thesecond conductive layer and the conductive sidewall.

[0050] The above-mentioned object of the present invention is achievedby a layer structure comprising:

[0051] a first conductive layer;

[0052] an insulating layer formed on the first conductive layer andhaving a contact hole, the first conductive layer being exposed throughthe contact hole;

[0053] a second conductive layer formed on the insulating layer andhaving a first opening having a width larger than that of the contacthole;

[0054] a third conductive layer formed on the insulating layer exposedthrough the first opening and the second conductive layer and formedaround an inner wall of the second conductive layer defining the firstopening, the third conductive layer defining a second opening having awidth substantially equal to that of the contact hole, the secondopening being continuously connected to the contact hole;

[0055] a barrier layer formed on the third conductive layer and thefirst conductive layer exposed through the contact hole; and

[0056] a fourth conductive layer formed on the barrier layer, thebarrier layer preventing the fourth conductive layer from reacting withthe third conductive layer and the conductive sidewall.

[0057] The above-mentioned object of the present invention is alsoachieved by a layer structure comprising:

[0058] a first conductive layer;

[0059] an insulating layer formed on the first conductive layer andhaving a contact hole, the first conductive layer being exposed throughthe contact hole;

[0060] a second conductive layer formed on the insulating layer andhaving an opening having a width larger than that of the contact hole;

[0061] a conductive sidewall formed on the insulating layer exposedthrough the opening and formed around an inner wall of the secondconductive layer defining the opening, the conductive sidewall having awidth substantially equal to that of the contact hole; and

[0062] a third conductive layer formed on the second conductive layer,the conductive sidewall and the first conductive layer exposed throughthe contact hole,

[0063] wherein the third conductive layer comprises a material whichcauses no reaction with the second conductive layer and the conductivesidewall.

[0064] According to the present invention, there is also provided adynamic random access memory having any of the above-mentionedstructures.

[0065] According to the present invention, there is also provided afin-shaped capacitor and a method for producing such a fin-shapedcapacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Other objects, features and advantages of the present inventionwill become more apparent from the following detailed description whenread in conjunction with the accompanying drawings, in which:

[0067]FIG. 1A through FIG. 1H are cross-sectional views showing steps ofan improved method for producing a layer structure having a contact holeaccording to a first preferred embodiment of the present invention;

[0068]FIG. 2 is a cross-sectional view showing a second preferredembodiment of the present invention;

[0069]FIGS. 3A through 3D are cross-sectional views showing a thirdpreferred embodiment of the present invention;

[0070]FIG. 4 is a cross-sectional view showing a fourth preferredembodiment of the present invention;

[0071]FIG. 5 is a cross-sectional view showing a fifth preferredembodiment of the present invention;

[0072]FIGS. 6A through 6N are cross-sectional views showing steps of aDRAM production method according to a sixth preferred embodiment of thepresent invention;

[0073]FIG. 7 is a plan view of a DRAM produced by the sixth preferredembodiment of the present invention;

[0074]FIGS. 8A through 8E are cross-sectional views showing a seventhpreferred embodiment of the present invention;

[0075]FIGS. 9A and 9B are cross-sectional views showing a firstvariation of the sixth preferred embodiment of the present invention;

[0076]FIG. 10 is a cross-sectional view showing a second variation ofthe sixth preferred embodiment of the present invention;

[0077]FIGS. 11A through 11J are cross-sectional views showing an eighthpreferred embodiment of the present invention;

[0078]FIGS. 12A through 12G are cross-sectional views showing a ninthpreferred embodiment of the present invention;

[0079]FIGS. 13A through 13F are cross-sectional views showing avariation of the ninth preferred embodiment of the present invention;

[0080]FIGS. 14A through 14G are cross-sectional views showing amodification of the variation shown in FIGS. 13A through 13F; and

[0081]FIGS. 15A through 15J are cross-sectional views showing a tenthpreferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0082] A description will now be given of a first preferred embodimentof the present invention with reference to FIG. 1A through FIG. 1H.

[0083] Referring to FIG. 1A, a conductive layer 2 formed of, forexample, polysilicon, is formed on a base 1 formed of an insulator, suchas SiO₂. The polysilicon layer 2 is a word line of a DRAM, for example.An insulating layer 3 formed of, for example, BPSG(boron-phosphosilicate glass), is grown to, for example, 0.5 μm on theentire surface by a CVD process. The BPSG layer 3 is heated in a wetatmosphere at 850° C. for 10 minutes, and reflown, so that asubstantially flat surface of the BPSG layer 3 can be formed. Then, apolysilicon layer 4 is grown to, for example, 1000 angstrom by the CVDprocess. After that, a photoresist film 5 is coated, and etched by theconventional photolithography technique, so that the photoresist film 5functions as an etching resist having a hole pattern can be formed.Subsequently, the polysilicon layer 4 is selectively etched by an RIE(reactive ion etching) process in which a CCl₄/O₂ gas is used and thephotoresist film 5 functions as an etching mask. Thereby, a firstopening 6 having a width (diameter) approximately equal to 0.5 μm isformed in the polysilicon layer 4.

[0084] As shown in FIG. 1B, a polysilicon layer 7 is grown to, forexample, 1500 angstroms on the entire surface including the firstopening 6 by CVD. Then, as shown in FIG. 1C, the polysilicon layer 7 isselectively etched by the RIE process using a CCl₄/O₂ gas, so that asidewall 8 is formed on an inner wall (sidewall) of the first opening 6formed in the polysilicon layer 4. The sidewall 8 defines a secondopening 9 having a width approximately equal to 0.2 μm.

[0085] As shown in FIG. 1D, the BPSG layer 3 is selectively etched in anRIE process using a CHF₃/He gas in which the polysilicon layer 4 and thesidewall 8 function as masks. Thereby, a contact hole 10 through whichthe polysilicon layer 2 is partially exposed is formed in the BPSG layer3.

[0086] As shown in FIG. 1E, a photoresist film 11 is formed on theentire surface including the contact hole 10. Then, as shown in FIG. 1F,the entire surface of the photoresist film 11 is exposed and developed.During this process, a small amount of light enters a bottom portion ofthe contact hole 10. Thus, a part of the photoresist film 11 is left inthe contact hole 10. The polysilicon layer 4 and the sidewall 18 aredry-etched in a CF₄/O₂ plasma atmosphere in a state where thepolysilicon layer 2 is protected against dry etching due to theexistence of the photoresist film 11 in the contact hole 10. During thedry etching process, the polysilicon layer 4 and the sidewall 8 areisotropically etched. After that, the photoresist film 11 is removed inan O₂ plasma.

[0087] After that, an Al alloy (or Al) 12 is deposited on the uppersurface including the contact hole 10 by a sputtering process. Then, theAl alloy layer 12 is etched, so that a desired Al (or Al alloy) patternis formed. Thereby, the polysilicon word line 2 is connected to the Alalloy layer 12 via the contact hole 10. It will be noted that thecontact hole 10 has a width smaller than the feature scale limit of theconventional photolithographic technique. It will also be noted that theabove-mentioned production method is suitable for forming a contact holefor connecting the word line and the word-line shunt layer which isprovided for preventing the occurrence of a delay in transmitting asignal via the word line.

[0088] The BPSG layer 3 can be substituted for a stacked member in whicha PSG layer and an SiO₂ layer are alternately stacked. It is alsopossible to employ an alternative step instead of the step shown in FIG.1H. In the alternative step, after the polysilicon layer 4 and thesidewall 8 are removed, the BPSG layer 3 is reflowed by heating thedevice in an N₂ atmosphere at 850° C. for 20 minutes, so that an upperedge of the contact hole 10 is smoothly curved. The existence of such asmoothly curved upper edge of the contact hole 10 improves the coverageof the Al alloy layer 12.

[0089] A description will now be given of a second preferred embodimentof the present invention with reference to FIG. 2. A layer structureshown in FIG. 2 is the same as that shown in FIG. 1B except that an SiO₂layer 13 is formed on the polysilicon layer 4. More specifically, theSiO₂ film 13 is grown to, for example, about 200 angstroms on thepolysilicon layer 4 by CVD. Then, the photoresist film 5 shown in FIG.1A is formed on the entire surface. After that, the first opening 6 isformed in the SiO₂ layer 13 and the polysilicon layer 4. Then, thepolysilicon layer 7 is formed on the photoresist film 5 and in the firstopening 6 in the same way as shown in FIG. 1B. Then, the polysiliconlayer 7 is anisotropically etched in the vertical direction. The SiO₂layer 13 functions as an etching stopper during the step shown in FIG.1C, so that it is possible to prevent a decrease in the thickness of thepolysilicon layer 4. Further, it becomes easy to detect the end ofetching since the SiO₂ layer 13 is exposed. It will be noted that theSiO₂ layer 13 is removed together with the BPSG layer 3 during the stepshown in FIG. 1E. Thus, it is not necessary to provide a special step toremove the SiO₂ layer 13.

[0090] A description will now be given of a third preferred embodimentof the present invention with reference to FIGS. 3A through 3C, in whichthose parts which are the same as those shown in the previous figuresare given the same reference numerals.

[0091] Referring to FIG. 3A, the BPSG layer 3 is grown to, for example,0.5 μm on the entire surface including the polysilicon layer (word line)2 by CVD. Next, the polysilicon layer 4 is grown to, for example, 1000angstroms by CVD. Then, the photoresist film 5 is coated, and patternedby the conventional photolithography technique, so that a hole patternhaving a width approximately equal to 0.5 μm is formed in thephotoresist film 5. After that, the polysilicon layer 4 is selectivelyremoved by an RIE process using a CCl₄/O₂ gas in which the photoresistfilm 5 serves as a mask, so that the first opening 6 is formed in thepolysilicon layer 4.

[0092] As shown in FIG. 3B, a polysilicon layer 14 is selectively grownon the upper surface of the polysilicon layer 4 and a side surfacethereof by a CVD process in which the device is maintained at 650° C.and an SiH₄+HCl+H₂ gas is used. The polysilicon layer 14 defines asecond opening 15 having a width smaller than that of the first opening6. It is easy to control the thickness of the polysilicon layer 14, thatis, easy to control the width of the second opening 15.

[0093] Then, as shown in FIG. 3C, the BPSG layer 3 is removed via thesecond opening 15 by an RIE process using a CHF₃/He gas, so that thecontact hole 10 is formed and the polysilicon layer 2 is partiallyexposed through the contact hole 10. Finally, a stakced layer 16 fomedof a Ti/TiN layer 16 is formed on the polysilicon layer 14, and an Alalloy (or Al) layer 17 is formed on the stacked layer 16, as shown inFIG. 3D. The stacked laye 16 will be described in detail later.

[0094] A description will now be given of a fourth preferred embodimentof the present invention with reference to FIG. 4, in which those partswhich are the same as those shown in the previous figures are given thesame reference numerals. In the step shown in FIG. 1G, the polysiliconlayer 4 and the sidewall 8 are removed, on the other hand, according tothe fourth embodiment of the present invention, as shown in FIG. 4, thepolysilicon layer 4 and the sidewall 8 are not removed, but left on theBPSG layer 3. After the layer structure shown in FIG. 1D is obtained,the stacked layer 16 is formed on the entire surface including thepolysilicon layer 4, the sidewall 8 and the exposed surface of thepolysilicon layer 2 by CVD, for example. The stacked layer 16 consistsof a Ti layer having a thickness of 200 angstroms and a TiN layer havinga thickness of 1000 angstroms. Hereafter, the stacked layer 16 isreferred to as a Ti/TiN layer 16. After the Ti/TiN layer 16 is formed,the Al alloy (or pure Al) 17 is deposited on the Ti/TiN layer 16 bysputtering. After that, the polysilicon layer 4, the Ti/TiN layer 16 andthe Al alloy layer 17 are patterned by etching.

[0095] It will be noted that if the Al alloy layer (or pure Al layer) 17is deposited directly on the polysilicon layer 4 and the polysiliconsidewall 8, it will easily react to silicon in the layer 4 and thesidewall 8 during a subsequent annealing process in which a protectioncover is formed, for example. The above reaction increases theresistance of the Al alloy layer 17. The Ti/TiN layer 16 functions as abarrier layer which prevents the above-mentioned reaction. The barrierlayer 16 is not limited to the Ti/TiN layer.

[0096] A description will now be given of a fifth preferred embodimentof the present invention with reference to FIG. 5, in which those partswhich are the same as those shown in the previous figures are given thesame reference numerals. The fifth embodiment shown in FIG. 5 has theleft polysilicon layer 4 and the polysilicon sidewall 8, and uses a W(tungsten) layer functioning as a wiring line instead of the Al alloy(or pure Al) layer 17 shown in FIG. 4. The use of the W layer 18 doesnot need the deposition of the Ti/TiN layer 16.

[0097] After the layer structure shown in FIG. 1D is obtained, the Wlayer 18 is grown to, for example, 5000 angstroms on the entire surfaceincluding the polysilicon layer 4, the polysilicon sidewall 8 and theexposed surface of the polysilicon layer 2 by CVD. The contact hole 10is filled with tungsten, so that the coverage of the W layer 18 can beimproved. It will be noted that it is easy to fill the contact hole 10with tungsten by CVD. It will be noted that tungsten has a pooradhession to BPSG or SiO 2. On the other hand, as shown in FIG. 5, the Wlayer 18 is formed on the polysilicon layer 4 and the polysiliconsidewall 18. Thus, the adhession problem can be solved.

[0098] A description will now be given of a sixth preferred embodimentof the present invention with reference to FIG. 6A through FIG. 6N. Thesixth preferred embodiment of the present invention provides a DRAMhaving a contact hole defined by a sidewall.

[0099] Referring to FIG. 6A, an interlayer isolation insulating layer 22is grown to, for example, 4000 angstroms on a p-type silicon substrate21 by a selective thermal oxidation process (alocal-oxidation-of-silicon process: LOCOS), in which a silicon nitridelayer is used as an oxidation-resistant mask. Next, the silicon nitridelayer serving as the oxidation-resistant mask is removed, so that activeareas in the p-type silicon substrate 21 are exposed. Then, a gateinsulating layer 23 having a thickness equal to, for example, 100angstroms is formed on the exposed surfaces of the p-type siliconsubstrate 21 by a thermal oxidation process. After that, a polysiliconlayer is grown to, for example, 1000 angstroms by CVD. Then, thepolysilicon layer is patterned by a resist process and RIE process inthe photolithography technique in which a CCl₄/O₂ gas is used. Thereby,word lines WL are formed. After that, As ions are introduced into thep-type silicon substrate 21 by an ion implantation process in which theword lines WL and the interlayer isolation insulating layer 2 functionas masks. Thereby, an n⁺-type source region 24 and an N⁺-type drainregion 25 of a transfer transistor of a memory cell are formed in thep-type silicon substrate 21. The dose of As ions is equal to, forexample, 1×10¹⁵ atoms/cm². During a subsequent thermal process, thesource and drain regions 24 and 25 are heated. After that, an insulatinglayer 26 formed of SiO₂ is grown to, for example, 1000 angstroms by CVD.

[0100] As shown in FIG. 6B, the SiO₂ insulating film 26 is selectivelyetched in an RIE process in which a CHF₃/H₂ gas is used, so that a bitline contact hole 24A is formed in the SiO₂ insulating film 26. It willbe noted that if a positional error occurs in the bit line contactwindow 24A and thus the word line WL is partially exposed, an exposedportion of the word line WL can be compensated for, as will be describedlater. Thus, it is sufficient to provide an alignment marginapproximately equal to 0.1 μm when the bit line contact window 24A isapproximately 0.5 μm in diameter. As will be indicated later, it ispreferable to remove a portion of the SiO₂ insulating layer 26 in ascribe area defined in a peripheral portion of a chip at the same timeas then the bit line contact hole 24A is formed.

[0101] As shown in FIG. 6C, an SiO₂ insulating layer 41 is grown to, forexample, 1000 angstroms on the entire surface by CVD.

[0102] After that, as shown in FIG. 6D, the SiO₂ insulating layer 41 isselectively etched by an anisotropic etching process, such as, an RIEprocess using a CHF₃/H₂ gas. By this RIE process, a sidewall SW1 havingan about 0.1 μm thickness is formed so that it surrounds a verticalinner wall of the bit line contact window 24A and a curved part of theSiO₂ insulating layer 26. The sidewall SW1 defines the width of the bitline contact hole 24A, which is approximately equal to 0.3 μm. It willbe noted that this dimension, 0.3 μm, is considerably smaller than thescale limit by the conventional photolithography technique(approximately 0.5 μm). The formation of the sidewall SW1 contributes toreducing the alignment margin. Even if the word line WL is partiallyexposed due to the positional error of the bit line contact window 24A,the sidewall 24 will completely cover the exposed surface of the wordline WL.

[0103] The above-mentioned contact hole forming process is distinguishedfrom a known self-alignment contact formation method. In theself-alignment contact formation method, an insulating layercorresponding to the SiO₂ insulating layer 26 and a polysilicon layerprovided for the word lines WL are patterned into an identical shape.Then, sidewalls are formed around windows. Thus, the windows areautomatically defined by the sidewalls, so that there is no need for anyalignment margin. Normally, the insulating film corresponding to theSiO₂ insulating layer 26 is 2000 angstroms thick, and the underlyingpolysilicon layer provided for forming the word lines WL is 1000angstron's thick. Thus, the sidewall is about 3000 angstrom high, and isa large step portion formed on the surface of the substrate. On theother hand, the process which has been described with reference to FIG.6D does not form such a great step surface portion. It should be notedthat the sidewall SW1 is also formed on a step portion on the surface ofthe SiO insulating film, so that the slope of the curved surface portionof the SiO₂ insulating layer 26 can be reduced.

[0104] It is necessary to etch only the SiO₂ insulating layer 41. As hasbeen described previously, the scribe area on the peripheral portion ofthe chip is exposed during the process shown in FIG. 6B. Since the SiO₂layer 41 is formed on the scribe area, etching is stopped when thescribe area which is a part of the p-type silicon substrate 21 appears.This judgment of whether or not the scribe area has appeared can becarried out by detecting a change of a plasma emitting state during theRIE process, or by detecting the film thickness of the scribe area bymeans of a laser interference instrument.

[0105] Referring to FIG. 6E, a polysilicon layer is grown to, forexample, 500 angstroms on the entire surface by CVD. Then, As ions areintroduced into the polysilicon layer by an ion implantation process inwhich the dose of As ions is equal to 1×10¹⁵ atoms/cm². After that, aWSi₂ film is formed to, for example, 500 angstroms on the impurity dopedpolysilicon layer by CVD. Then, the WSi₂ layer and the impurity dopedpolysilicon layer are patterned by an RIE process using a CCl₄/O₂ gas,so that a bit line BL having a two-layer structure is formed.

[0106] As shown in FIG. 6F, an insulating layer 27 formed of Si₃N₄, aspacer layer 28 formed of SiO₂ and a polysilicon layer 29′ which forms apart of a storage electrode (fin electrode) of a stacked capacitor aregrown in this order by CVD. The Si₃N₄ insulating layer 27, the SiO₂spacer layer 28 and the polysilicon layer 29′ are, for example, 1000,500 and 1000 angstroms, respectively. It will be noted that thepolysilicon layer 29′ plays the important role, as will be describedlater.

[0107] As shown in FIG. 6G, the polysilicon layer 29′ is selectivelyetched by the resist process and RIE process using a CCl₄/O₂ gas in theconventional photolithography technique, so that an opening 29A havingthe same pattern as the storage electrode contact window is formed inthe polysilicon layer 29′. During the selective etching process, it ispreferable to remove a part of the polysilicon layer 29′ on the scribearea in the chip peripheral region. The opening 29A has a widthapproximately equal to 0.5 μm, which is the scale limit attained by theconventional photolithography technique.

[0108] As shown in FIG. 6H, a polysilicon layer 32 a is grown to, forexample, 1000 angstroms by CVD. Then, as shown in FIG. 6I, thepolysilicon layer is anisotropically etched by an RIE process using aCCl₄/O₂ gas. Thereby, a sidewall 32 formed of polysilicon around theinner surface of the opening 29A in the polysilicon layer is left on theSiO₂ spacer layer 28. The sidewall 32 is approximately 0.1 μm thick. Asa result, the opening 29A is reshaped into an opening 32A having a widthof about 0.3 μm. This dimension of the reshaped opening 29A is smallerthan the scale limit by the conventional photolithography technique.

[0109] The polysilicon layer 29′ and the polysilicon sidewall 32function as masks when the underlying insulating layers are etched toform the storage electrode contact window. It should be noted that thereis no special limitation on the formation of the polysilicon layer 29′and the polysilicon sidewall 32, since they are formed of polysilicon.It should also be noted that the polysilicon layer 29′ and thepolysilicon sidewall 32 are not removed during a subsequent process, andare utilized as parts of the storage electrode of the stacked capacitor,as will be described in detail later.

[0110] As shown in FIG. 6J, the SiO₂ aaaspacer layer 28, the Si₃N₄insulating layer 27, the SiO₂ insulating layer 26 and the SiO₂ gateinsulating layer 23 are selectively etched by an RIE process in which aCHF₃/H₂ is used and the polysilicon layer 29′ and the polysiliconsidewall 32 function as the etching masks. By the RIE process, a storageelectrode contact hole 25A is formed in the above-mentioned layers, sothat the n⁺-type drain region 25 is partially exposed.

[0111] As shown in FIG. 6K, a polysilicon layer 29″ is grown to, forexample, 500 angstroms by CVD. A part of the polysilicon layer 29″completely covers the inner wall of the storage electrode contact window25A and the exposed surface of the n⁺-type drain region 25. It isimportant to form the polysilicon layer 29″ in total contact with theSi₃N₄ insulating layer 27. Then, As ions are introduced into thepolysilicon layers 29″ and 29′ by an ion implantation process in whichthe dose of the As ions is equal to, for example, 8×10¹⁵ atoms/cm². Bythis ion implantation process, each of the polysilicon layers 29″ and29′ has a reduced resistance. It will be noted toat the layersconsisting of the polysilicon layers 29′ and 29″ and the sidewall 32 isthicker than the vertically extending portion of the polysilicon layer29″.

[0112] Referring to FIG. 6L, a spacer layer 33 formed of SiO₂ is grownto, for example, 500 angstroms on the entire surface by CVD. After that,the SiO₂ spacer layer 33 is selectively etched by the resist process andRIE process using a CHF₃/H₂ gas in the conventional photolithographytechnique. By the RIE process, an opening 33A having a belt shape isformed in the SiO₂ spacer layer 33. It is sufficient to form the opening33A so that it is wider than the storage electrode contact window 25A,because the opening 33A is used for stacking a polysilicon layer (fin)on the integrated polysilicon layer consisting of the layers 29″ and 29′and the polisilicon sidewall 32.

[0113] Referring to FIG. 6M, a polysilicon layer is grown to, forexample, 1000 angstroms by CVD. After that, As ions are introduced intothe polysilicon layer by an ion implantation process in which the doseof As ions is equal to, for example, 1×10¹⁵ atoms/cm². Thereby, theresistance of the polysilicon layer is reduced. After that, the abovepolysilicon layer, the SiO₂ spacer layer 33, and the polysilicon layers29″ and 29′ are patterned into an electrode shape by the photoresistprocess and RIE process using a gas of CCl₄+O₂ or CHF₃+H₂. Thereafter,the SiO spacer layer 33 and the SiO₂ spacer layer 28 are completelyremoved by an etching process in which the device is placed in an HFetchant. Thereby, polysilicon fins 292 and 291 forming a storageelectrode 25 of the stacked capacitor are formed. The fin 292 has abottom contact area wider than the contact hole 25A shown in FIG. 6J.

[0114] As has been described previously, the wall of the Si₃N₄insulating layer 27 which is a part of the storage electrode contactwindow 25A completely makes contact with the polysilicon layer 29′, sothat there is no possibility that the SiO₂ insulating layer 26 and theSiO₂ interlayer isolation insulating layer 22 are damaged.

[0115] After that, as shown in FIG. 6N, a dielectric film 36 around anexposed surface of the storage electrode 29 is formed, and a cell plate37 (opposed electrode) is formed so that it covers the entire surface.The dielectric film 36 is formed of, for example, Si₃N₄. The stackedcapacitor is made up of the storage electrode 29, the dielectric film 36and the cell plate 37. Then, a PSG layer 38 is formed on the entiresurface, and word-line shunt layers 39 formed of, for example, an Alalloy, are formed on the PSG layer 38. FIG. 7 is a plan view of the DRAMfabricated by the above-mentioned production process. In FIG. 7, WL1 andWL2 indicate word lines, and BL1 and BL2 indicate bit lines.

[0116] The word-line shunt layers 39 are connected to the correspondingword lines WL via contact holes (not shown for the sake of simplicity).It is preferable to form such contact holes by the aforementioned firstthrough fifth embodiments of the present invention.

[0117] It can be seen from FIG. 6K that the lowermost polysilicon fin 29₁ has the sidewall 32, and the polysilicon layers 29′ and 29″. Thepolysilicon layer 29″ is thicker than the polysilicon layer 29′, and thelargest thickness of the sidewall 32 is approximately equal to thethickness of the polysilicon layer 29′.

[0118] A description will now be given of an eighth embodiment of thepresent invention with reference to FIGS. 8A through 8E, in which thoseparts which are the same as those shown in the previous figures aregiven the same reference numerals. The eighth embodiment of the presentinvention utilizes the steps which have been described with reference toFIGS. 6A through 6L. After the step related to FIG. 6L, a step shown inFIG. 8A is carried out. A polysilicon layer is grown to, for example,1000 angstroms on the entire surface.

[0119] After that, as shown in FIG. 8B, an insulating layer 34 formed ofSiO₂ is grown to, for example, 2000 angstroms by CVD. Then, the SiO₂insulating film 34 is patterned into the shape of the storage electrodeby the resist process and RIE process using a CHF₃/H₂ gas in thephotolithography technique, so that openings are formed in the SiO₂insulating film 34. Each of the openings is approximately 0.5 μm wide,which corresponds to the scale limit of the conventionalphotolithography technique.

[0120] Then, an insulating layer 35 formed of SiO₂ is grown to, forexample, 1000 angstroms on the entire surface by CVD. Thereafter, theSiO₂ insulating layer 35 is anisotropically etched by an RIE processusing a CHF₃ and H₂ gas. Thereby, sidewalls 35 are formed around innerwalls of the openings in the SiO₂ layer 34, and the rest thereof isremoved. Each sidewall 35 defines an opening 35A having a widthapproximately equal to 0.3 μm, which is smaller than the scale limit ofthe conventional photolithography technique.

[0121] Then, as shown in FIG. 8C, the polysilicon layer 42, the SiO₂spacer layer 33, and the polysilicon layers 29″ and 29′ are patternedinto the shape of the storage electrode by an RIE process in which aCHF₃/H₂ gas is used and the SiO₂ insulating layer 34 and the SiO₂sidewalls 15 function as etching masks. It should be noted that thedistance between opposite portions of the polysilicon layer 42 isapproximately 0.3 μm. Similarly, the distance between opposite portionsof the polysilicon layer consisting of the polysilicon layer 29″ and 29′is also approximately 0.3 μm. This means that the adjacent storageelectrodes are very close to each other, and thus the surface area ofeach storage electrode is increased, so that each stacked capacitor canhave an increased capacitance.

[0122] It will be noted that during etching of the SiO₂ spacer layer 33,the SiO₂ insulating layer 34 and the SiO₂ sidewalls 35 serving asetching masks are also etched. From this point of view, it is necessaryfor the layer 34 and the sidewalls 35 to have a sufficient thickness.Further, a special step to remove the SiO₂ insulating layer 34 and theSiO₂ sidewalls 35 is not needed because the SiO₂ insulating layer 34 andthe sidewalls 35 are removed during a subsequent step in which thedevice is placed in an HF etchant, as shown in FIG. 8D.

[0123] After that, a process identical to that which has been describedwith reference to FIG. 6N is carried out. FIG. 8E shows a DRAMfabricated according to the seventh preferred embodiment of the presentinvention. A storage electrode 40 has two stacked polysilicon fins 40 ₁and 40 ₂. The polysilicon fin 401 corresponds to the patternedpolysilicon layers 29″ and 29′ and the polysilicon sidewall 32, and thepolysilicon fin 402 corresponds to the patterned polysilicon layer 42.It can be seen from FIG. 6N and FIG. 8E that the adjacent stackedcapacitors shown in FIG. 8E are closer to each other than those shown inFIG. 6N.

[0124] A description will now be given of a first variation of theaforementioned sixth preferred embodiment of the present invention, withreference to FIGS. 9A and 9B, in which those parts which are the same asthose shown in the previous figures are given the same referencenumerals. The first variation has a storage electrode having only thepolysilicon fin 29 ₁ which consists of the polysilicon layers 29″ and29′ and the polysilicon sidewall 32. After the step which has beendescribed with reference to FIG. 6K, the polysilicon layer consisting ofthe polysilicon layers 29″ and 29′ and the polysilicon sidewall 32 ispatterned into the shape of the storage electrode. After that, thedevice is placed in an HF etchant, so that the insulating layer 28 iscompletely removed, as shown in FIG. 9A. Then, the process which hasbeen described previously with reference to FIG. 6N is carried out, sothat a DRAM shown in FIG. 9B can be obtained. It 1 is noted that theinsulating layer 27 can be formed of SiO₂ or Si₃N₄. As shown in FIG. 9B,the fin 29 ₁ is thicker than a vertically extending portion of thestorage electrode.

[0125]FIG. 10 illustrates a second variation of the aforementioned sixthpreferred embodiment of the present invention. In FIG. 10, those partswhich are the same as those shown in the previous figures are given thesame reference numerals. The polysilicon fin 29 ₁ consisting of thepolysilicon layers 29″ and 29′ and the polysilicon sidewall 32 is formeddirectly on the insulating layer 27 formed of SiO₂ or Si₃N₄. Thepolysilicon layer 29′ shown in FIG. 6F is grown on the insulating layer27 without forming the insulating layer 28. Then, the same steps as hasbeen described with reference to FIGS. 6G through 6K and FIG. 6N arecarried out. It is also possible to form the polysilicon fin 29 ₂ on thepolysilicon fin 29 ₁ in the same way as has been described withreference to FIGS. 6L and 6M.

[0126] A description will now be given of an eighth preferred embodimentof the present invention with reference to FIGS. 11A through 11J, inwhich those parts which are the same as shown shown in the previousfigures are given the same reference numerals. A structure shown in FIG.11B is the same as that shown in FIG. 6E. Steps to obtain the structureshown in FIG. 11B are the same as those which have been described withreference to FIGS. 6A through 6E.

[0127] As shown in FIG. 11C, the Si₃N₄ insulating layer 27, the SiO₂spacer layer 28, the impurity-doped polysilicon layer 29′, a spacerlayer 45 formed of SiO₂ and an impurity-doped polysilicon layer 46′ areformed in this order by CVD. For example, each of these layers is 500angstorms thick. Then, the polysilicon layer 46′, the SiO₂ spacer layer45 and the polysilicon layer 29′ are selectively etched by the resistprocess and the RIE process, so that an opening 29A having a thicknessequal to, for example, 0.6 μm is formed therein. During the above RIEprocess, a CCl₄/O₂ gas is used for the polysilicon layers 46′ and 29′,and a CHF₃/He gas is used for the SiO₂ spacer layer 45.

[0128] As shown in FIG. 11D, a polysilicon layer 47′ is grown to, forexample, 2000 angstorms on the entire surface by CVD. After that, asshown in FIG. 11E, the polysilicon layer 47′ is anisotropically etchedby an RIE process in which a CCl₄/O₂ gas or an HBr/He gas is used.Thereby, a polysilicon sidewall 47 is formed around an inner surface ofthe opening 29A, and the remaining portion of the polysilicon layer 47′is removed. The sidewall 47 defines a new opening 46A having a widthapproximately equal to 0.2-0.3 μm, which is smaller than the width ofthe opening 29A shown in FIG. 11C.

[0129] After that, as shown in FIG. 11F, the SiO₂ spacer layer 28, theSi₃N₄ insulating layer 27, the SiO₂ insulating layer 26 and the SiO₂gate insulating layer 23 are partially removed by an RIE process inwhich a CHF₃/He gas is used and the polysilicon layer 46′ and thepolysilicon sidewall 47 function as etching masks. By this RIE process,the surface of the n⁺-type drain region 25 is partially exposed througha contact hole 28A.

[0130] It should be noted that the width of the opening 46A is verysmall and equal to about 0.2-0.3 μm, and that the polysilicon layer 46′and the polysilicon layer 47 functioning as the etching masks form apart of the storage electrode without being removed. Thus, it is notnecessary to provide a special step to remove the polysilicon layer 46′and the polysilicon sidewall 47 functioning the etching masks.

[0131] As shown in FIG. 11G, a polysilicon layer 46″ is grown to, forexample, 500 angstroms by CVD. During this step, the polysilicon layers46″ and 46′ as well as the polysilicon sidewall 47 are integrated.

[0132] Then, as shown in FIG. 11H, the polysilicon layers 46″ and 46′,the SiO₂ spacer layer 45, and the polysilicon layer 29′ are patternedinto the shape of the storage electrode in this order by the resistprocess using a single mask and the RIE process in the conventionalphotolithography process.

[0133] After that, as shown in FIG. 11I, the device shown in FIG. 11H isplaced in an HF etchant, so that the exposed SiO₂ insulating layers areisotropically etched, so that a storage electrode 50 having twopolysilicon fins 50 ₁ and 50 ₂ is formed. The fin 50 ₁ is formed of thepatterned polysilicon layer 29′, and the fin 502 is formed of thepatterned polysilicon layers 46″ and 46′. The fins 50 ₁ and 50 ₂ areconnected by the polysilicon sidewall 47. The polysilicon layer 46″which is a part of the fin 50 ₂ vertically extends from its portion onthe polysilicon layer 46′ and makes contact with the n⁺-type drainregion 25. A vertical portion 50 ₃ of the storage electrode 50 consistsof the polysilicon sidewall 47 and the polysilicon layer 46″. Thevertical portion 50 ₃, the polysilicon layer 46″, and the fin 50 ₂ havemutually different thicknesses t₁, t₂ and t₃, respectively. The verticalportion 503 is thicker than the polysilicon layer 46″ and the fin 50 ₂.

[0134] Finally, as shown in FIG. 11J, the dielectric film 36, the cellplate 37, the PSG passivation layer 38 and the word-line shut layers 39are formed in the same way as has been described with reference to FIG.6N.

[0135] A description will now be given of a ninth preferred embodimentof the present invention with reference to FIGS. 12A through 12G, inwhich those parts which are the same as those shown in the previousfigures are given the same reference numerals.

[0136] Production steps shown in FIGS. 12A and 12B are carried out inthe same way as those shown in FIGS. 11A and 11B. After that, as shownin FIG. 12C, the Si₃N₄ insulating layer 27, the SiO₂ spacer layer 28,the impurity-doped polysilicon layer 29′, the SiO₂ spacer layer 45 andthe impurity-doped polysilicon layer 46′ are formed in this order byCVD. Each of these layers is 500 angstroms thick, for example. Then, thepolysilicon layer 46′, the SiO₂ spacer layer 45, the polysilicon layer29′ and the SiO₂ spacer layer 28 are selectively etched by the resistprocess and RIE process, so that an opening 28A is formed therein. Itwill be noted that the SiO₂ layer 28 is etched as shown in FIG. 12C,while the SiO₂ layer 28 shown in FIG. 11C is not etched.

[0137] After that, as shown in FIG. 12D, a polysilicon layer 47′ isgrown to, for example, 2000 angstorms by CVD. After that, as shown inFIG. 12E, the polysilicon layer 47′ is selectively etched by an RIEprocess using a CCl₄/O₂ gas, so that a polysilicon sidewall 47 a isformed so that it surrounds the inner wall of the opening 28A. Theremaining portion of the polysilicon layer 47′ is completely removed.The polysilicon sidewall 47 a defines a new opening 46A narrower thanthe opening 28A.

[0138] Subsequently, as shown in FIG. 12F, the Si₃N₄ insulating layer27, the SiO₂ insulating layer 26 and the SiO₂ gate insulating layer 23are selectively etched by an RIE process in which a CHF₃/He gas is usedand the polysilicon layer 46′ and the sidewall 47 a function as etchingmasks. By this RIE process, the surface of the n⁺-type drain region 25is partially exposed through a through hole 27A having the same width asthe opening 46A. After that, the aforementioned production steps arecarried out, so that a DRAM shown in FIG. 12G can be obtained.

[0139] The length of the sidewall 37 a used in the ninth embodiment ofthe present invention is greater than that of the sidewall 37 used inthe eighth embodiment of the present invention. Thus, the sidewall 47 afunctions as the mask more stably than the sidewall 47. On the otherhand, the distance between the sidewall 37 a and the word line WL iscloser than the corresponding distance obtained in the eighth embodimentof the present invention. Thus, the breakdown voltage of the DRAM shownin FIG. 12G is slightly smaller than that of the DRAM shown in FIG. 11J.

[0140] A description will now be given of a variation of the ninthpreferred embodiment of the present invention with reference to FIGS.13A through 13F, in which those parts which are the same as those shownin the previous figures are given the same reference numerals. FIGS. 13Aand 13B are the same as FIGS. 11A and 11B. Then, as shown in FIG. 13C,the Si 3N4 insulating layer 27, the SiO₂ layer 28, the impurity-dopedpolysilicon layer 29′, the SiO₂ spacer layer 45 and the impurity-dopedpolysilicon layer 46′ are formed in this order by the aforementionedprocess. Then, an SiO₂ insulating layer 48 is grown to, for example, 200angstroms by CVD.

[0141] Then, by using the resist process and the RIE process in thephotolithography process, the SiO₂ layer 48, the polysilicon layer 46′,the SiO₂ spacer layer 45, the polysilicon layer 29′ and the SiO₂ spacerlayer 28 are selectively removed, so that the surface of the Si₃N₄ layer27 is partially exposed through the opening 28A.

[0142] Then, as shown in FIG. 13D, the polysilicon layer 47′ is grownto, for example, 2000 angstorms by CVD. After that, as shown in FIG.13E, the polysilicon layer 47′ is selectively etched by RIE, so that awidewall 42 b is formed around an inner wall of the opening 28A.

[0143] After that, as shown in FIG. 13F, the Si₃N₄ layer 27, the SiO₂layer 26 and the SiO₂ gate insulating layer 23 are selectively etchedvia the opening defined by the sidewall 47 b. The SiO₂ layer 48 isremoved at the same time as the SiO₂ insulating layer 26 is removed.

[0144] It will be noted that the SiO₂ layer 48 functions to protect thepolysilicon layer 46′ against the RIE process of forming the sidewall 47b. Further, the SiO₂ layer 48 functions as the mask more stably duringthe time when the Si₃N₄ insulating layer 27 is being etched.

[0145] A description will now be given of a modification of thevariation shown in FIGS. 13A through 13F, with reference to FIGS. 14Athrough 14G, in which those parts which are the same as those shown inthe previous figures are given the same reference numerals. FIGS. 14Aand 14B are the same as FIGS. 11A and 11B, respectively.

[0146] After forming the bit line BL, as shown in FIG. 14C, an SOG (spinon glass) layer 49 is formed on the entire surface so that the surfaceof the SOG layer 49 is substantially flat enough to prevent the growthof residuum during a subsequent process. There is a possibility thatresiduum may be formed on a rough surface after the selective etchingprocess. For example, in the variation which has been described withreference to FIGS. 13A through 13F, the SiO₂ layer 48 may be partiallyleft on a rough surface portion of the polysilicon layer 46′. For thesake of simplicity, FIG. 14C shows that the SOG layer 49 is completelyflat. It can be seen from FIG. 14C, the SOG layer 49 absorbs a roughnessof the surface shown in FIG. 14B. It is also possible to form a PSGreflow layer instead of the SOG layer 49. After that, the layers 28, 29′45, 46′ and 48 are formed in the same way as has been describedpreviously. Then, these layers are selectively etched, so that theopening 28A is formed, as shown in FIG. 14C.

[0147] Then, as shown in FIG. 14D, the polysilicon layer 47′ is grownto, for example, 2000 angstroms by CVD, and selectively etched by theRIE process, so that a sidewall 47 b is formed, as shown in FIG. 14E.Thereafter, as shown in FIG. 14F, the Si₃N₄ insulating layer 27, the SOGlayer 49, the sio₂ layer 26 and the SiO₂ layer 23 are selectivelyetched, so that the n⁺-type drain region 25 is partially exposed throughthe opening 27A. Finally, a DRAM shown in FIG. 14G is fabricated by theaforementioned process which has been described with reference to FIG.6N.

[0148] A description will now be given of a tenth preferred embodimentof the present invention with reference to FIGS. 15A through 15J, inwhich those parts which are the same as those shown in the previousfigures are given the same reference numerals. FIGS. 15A and 15B are thesame as FIGS. 11A and 11B, respectively.

[0149] Referring to FIG. 11C, after forming an Si₃N₄ layer 62 by CVD,three bilayer structures, each having an SiO₂ insulating layer having athickness of 500 angstroms and a polysilicon layer having a thickness of500 angstroms, are successively grown by CVD. The first bilayerstructure consists of an SiO₂ insulating layer 63 and a polysiliconlayer 64. The second bilayer structure consists of an SiO₂ insulatinglayer 65 and a polysilicon layer 66. The third bilayer structureconsists of an SiO₂ insulating layer 67 and a polysilicon layer 68.After that, an SiO₂ insulating layer 69 having a thickness of 100angstroms, a polysilicon layer 70 having a thickness of 2000 angstormsand an SiO₂ insulating layer 71 having a thickness of 100 angstroms aresuccessively grown in this order by CVD. Then, a photoresist film 72having a window pattern is placed on the SiO₂ insulating layer 71, andthe SiO₂ insulating layer 71 and the polysilicon layer 70 are etched, sothat an opening 70A is formed. The size of the opening 70A isapproximately 0.5 μm, which is the scale limit in the conventionalphotolithography technique.

[0150] Referring to FIG. 15D, the photoresist film 72 is removed, and apolysilicon layer is grown to, for example, 1500 angstroms on the entiresurface. Then, the polysilicon layer is anisotropically etched by an RIEprocess using an HBr/He gas, so that a polysilicon sidewall 74 is formedaround an inner wall of the opening 70A. The polysilicon sidewall 74defines a new opening 70B having a size approximately equal to 0.2 μm.

[0151] After that, as shown in FIG. 15E, the SiO₂ insulating layer 69and the polysilicon layer 68 are anisotropically etched by an RIEprocess in which the polysilicon layer 70 and the sidewall 74 functionas etching masks. During the time when the SiO₂ insulating layer 69 isbeing etched, the SiO₂ insulating layer 71 is removed. Further, duringthe time when the polysilicon layer 68 is being etched, the polysiliconlayer 70 decreases by approximately 700 angstroms, so that a portionthereof having a thickness of about 1300 angstroms is left. After that,the SiO₂ insulating layer 67 is removed in an RIE process using aCHF₃/H₂ gas in which the polysilicon layer 70 and the sidewall 74function as etching masks. During this etching process, there is littledecrease in the thicknesses of the polysilicon layer 70 and the sidewall74 because the CHF₃/H₂ gas acts to SiO₂ greatly. After that, thepolysilicon layer 66 and the SiO₂ insulating layer 65 are removed in thesame way as has been described above. During this etching process, eachof the polysilicon layer 70 and the sidewall 74 decreases by about 700angstroms, so that they are approximately 600 angstroms thick.

[0152] As shown in FIG. 15F, the polysilicon layer 64 is removed by RIE.During this RIE process, the polysilicon layer 70 and the sidewall 74are also removed. It will be noted that the SiO₂ insulating layer 69prevents the underlying polysilicon layer 68 from being etched even ifover-etching is carried out. It is preferable to carry out over-etchingso that the polysilicon layer 70 and the sidewall 74 are completelyremoved.

[0153] Then, as shown in FIG. 15G, the SiO₂ insulating layer 63 isremoved in an etching process in which the polysilicon layer 68functions as a mask. During this etching, the SiO insulating layer 69 is2 also removed. Subsequently, the Si 3N4 insulating layer 62 is etched,and the SiO₂ insulating layer 26 and SiO₂ gate insulating layer 23 areetched. Thereby, a window formed in the layers 68 through 23 is formed,as shown in FIG. 15G.

[0154] Then, referring to FIG. 15H, a polysilicon layer 75 is grown to,for example, 500 angstroms on the entire surface including the windowshown in FIG. 15G. After that, the polysilicon layers 75 and 68, theSiO₂ insulating layer 67, the polysilicon layer 66, the SiO₂ insulatinglayer 65, and the polysilicon layer 64 are patterned into the shape ofthe storage electrode. Thereby, a device shown in FIG. 15H is formed.

[0155] After that, as shown in FIG. 15I, the device shown in FIG. 15H isplaced in an HF etchant, so that the SiO₂ insulating layers 67, 65 and63 are isotropically etched and completely removed. By this step, astorage electrode 90 can be obtained. The storage electrode 90 has afirst polysilicon fin 90 ₁ formed of the patterned polysilicon layer 64,a second polysilicon fin 90 ₂ formed of the patterned polysilicon layer66, and a third polysilicon fin 90 ₃ having the patterned polysiliconlayers 68 and 75, and a vertical connecting portion formed of thepolysilicon layer 75. The third polysilicon fin 90 ₃ is thicker than thefirst and second polysilicon fins 90 ₁ and 90 ₂.

[0156] After that, the aforementioned processes are carried out for thedevice shown in FIG. 15I, so that a DRAM shown in FIG. 15J can beformed. It is possible to apply the teachings shown in FIGS. 13A through13F to the tenth embodiment of the present invention. It is alsopossible to form the lowermost fin9-₁ directly on the insulating layer62. In this case, the insulating layer 62 can be formed of SiO₂.

[0157] The present invention is not limited to the specificallydisclosed embodiments, and variations and modifications may be madewithout departing from the scope of the present invention.

What is claimed is:
 1. A method of forming a structure having a contacthole comprising the steps of: (a) forming an insulating layer on a firstconductive layer; (b) forming a second conductive layer on saidinsulating layer; (c) forming an opening in said second conductivelayer; (d) forming a conductive sidewall around an inner wall of saidfirst conductive layer defining said opening; (e) selectively etchingsaid insulating layer in a state where said second conductive layer andsaid conductive sidewall function as etching masks, so that said contacthole having a width smaller than that of said opening and defined bysaid conductive sidewall is formed, and said first conductive layer isexposed through said contact hole; and (f) removing said secondconductive layer and said conductive sidewall.
 2. A method as claimed inclaim 1, wherein said methd comprises, between said step (e) and saidstep (f), the steps of: (e-1) forming an etching resist on said firstconductive layer exposed through said contact hole, said secondconductive layer and said conductive sidewall; and (e-2) removing only apart of said etching resist on said second conductive layer and saidconductive sidewall so that said first conductive layer exposed throughsaid contact hole is protected by said etching resist.
 3. A method asclaimed in claim 2, wherein said step (e-2) comprises: projecting lightonto said etching resist; and developing said etching resist so that apart of said etching resist is left on said first conductive layerexposed through said contact hole.
 4. A method as claimed in claim 1,wherein: said method further comprises the step of forming an etchingstopper layer on said second conductive layer; and said etching stopperlayer protects said second conductive layer during said step (d), sothat the thickness of said second conductive layer can be prevented frombeing reduced during said step (d).
 5. A method as claimed in claim 1,wherein said method further comprises the step of forming a thirdconductive layer on said insulating layer and in contact with said firstconductive layer exposed through said contact hole.
 6. A method asclaimed in claim 1, wherein said first conductive layer comprisespolysilicon.
 7. A method as claimed in claim 1, wherein: said secondconductive layer comprises polysilicon; and said conductive sidewallcomprises polysilicon.
 8. A method as claimed in claim 1, wherein saidmethod further comprises the step of heating said insulating layer sothat said insulating layer is reflown and an edge portion of saidinsulating layer defining an upper portion of said contact hole isgradually curved.
 9. A method of forming a structure having a contacthole comprising the steps of: (a) forming an insulating layer on a firstconductive layer; (b) forming a second conductive layer on saidinsulating layer; (c) forming an opening in said second conductivelayer; (d) forming a conductive sidewall around an inner wall of saidfirst conductive layer defining said opening; (e) selectively etchingsaid insulating layer in a state where said second conductive layer andsaid conductive sidewall function as etching masks, so that said contacthole having a width smaller than that of said opening and defined bysaid conductive sidewall is formed on said insulating layer and saidfirst conductive layer is exposed through said contact hole; (f) forminga barrier layer on said second conductive layer, said conductivesidewall and said first conductive layer exposed through said contacthole; and (g) forming a third conductive layer on said barrier layer,said barrier layer preventing said third conductive layer from reactingwith said second conductive layer and said conductive sidewall.
 10. Amethod as claimed in claim 9, wherein: said barrier layer comprises abilayer structure having a titanium layer and a titanium nitride layer;and said third conductive layer comprises aluminum.
 11. A method asclaimed in claim 9, wherein: said second conductive layer comprisespolysilicon; and said conductive sidewall comprises polysilicon.
 12. Amethod of forming a structure having a contact hole comprising the stepsof: (a) forming an insulating layer on a first conductive layer; (b)forming a second conductive layer on said insulating layer; (c) formingan opening in said second conductive layer; (d) forming a conductivesidewall around an inner wall of said first conductive layer definingsaid opening; (e) selectively etching said insulating layer in a statewhere said second conductive layer and said conductive sidewall functionas etching masks, so that said contact hole having a width smaller thanthat of said opening and defined by said conductive sidewall is formed,and said first conductive layer is exposed through said contact hole;and (f) forming a third conductive layer on said second conductivelayer, said conductive sidewall and said member exposed through saidcontact hole, wherein: said second conductive layer comprisespolysilicon; said conductive sidewall comprises polysilicon; and saidthird conductive layer comprises tungsten.
 13. A method as claimed inclaim 12, wherein said contact hole is filled with tungsten of saidthird conductive layer.
 14. A method of forming a structure having acontact hole comprising the steps of: (a) forming an insulating layer ona first conductive layer; (b) forming a second conductive layer on saidinsulating layer; (c) forming a first opening in said second conductivelayer; (d) selectively growing a third conductive layer on said secondconductive layer and an inner wall of said second conductive layerdefining said first opening, so that a second opening defined by saidthird conductive layer and having a width smaller than that of saidfirst opening is formed; and (e) selectively etching said insulatinglayer in a state where said third conductive layer functions as anetching mask, so that said contact hole having a width substantiallyidentical to said second opening defined by said third conductive layeris formed, and said first conductive layer is exposed through saidcontact hole.
 15. A method as claimed in claim 14, wherein: said secondconductive layer comprises polysilicon; and said third conductive layercomprises polysilicon.
 16. A method as claimed in claim 14, wherein saidmethod further comprises the steps of: forming a barrier layer on saidthird conductive layer and said first conductive layer exposed throughsaid contact hole; and forming a fourth conductive layer on said barrierlayer, said barrier layer preventing said third conductive layer fromreacting with said fourth conductive layer.
 17. A layer structurecomprising: a first conductive layer; an insulating layer formed on saidfirst conductive layer and having a contact hole, said first conductivelayer being exposed through said contact hole; a second conductive layerformed on said insulating layer and having an opening having a widthlarger than that of said contact hole; a conductive sidewall formed onsaid insulating layer exposed through said opening and formed around aninner wall of said second conductive layer defining said opening, saidconductive sidewall having a width substantially equal to that of saidcontact hole; a barrier layer formed on said second conductive layer,said conductive sidewall and said first conductive layer exposed throughsaid contact hole; and a third conductive layer formed on said barrierlayer, said barrier layer preventing said third conductive layer fromreacting with said second conductive layer and said conductive sidewall.18. A layer structure as claimed in claim 17, wherein: said thirdconductive layer comprises aluminum; said first and second conductivelayers comprise polysilicon; and said conductive sidewall comprisespolysilicon.
 19. A layer structure as claimed in claim 17, wherein saidbarrier layer comprises a bilayer structure having a titanium layer anda titanium nitride layer.
 20. A layer structure comprising: a firstconductive layer; an insulating layer formed on said first conductivelayer and having a contact hole, said first conductive layer beingexposed through said contact hole; a second conductive layer formed onsaid insulating layer and having a first opening having a width largerthan that of said contact hole; a third conductive layer formed on saidinsulating layer exposed through said first opening and said secondconductive layer and formed around an inner wall of said secondconductive layer defining said first opening, said third conductivelayer defining a second opening having a width substantially equal tothat of said contact hole, said second opening being continuouslyconnected to said contact hole; a barrier layer formed on said thirdconductive layer and said first conductive layer exposed through saidcontact hole; and a fourth conductive layer formed on said barrierlayer, said barrier layer preventing said fourth conductive layer fromreacting with said third conductive layer and said conductive sidewall.21. A layer structure as claimed in claim 20, wherein: said fourthconductive layer comprises aluminum; and said first, second and thirdconductive layers comprise polysilicon.
 22. A layer structure as claimedin claim 20, wherein said barrier layer comprises a bilayer structurehaving a titanium layer and a titanium nitride layer.
 23. A layerstructure comprising: a first conductive layer; an insulating layerformed on said first conductive layer and having a contact hole, saidfirst conductive layer being exposed through said contact hole; a secondconductive layer formed on said insulating layer and having an openinghaving a width larger than that of said contact hole; a conductivesidewall formed on said insulating layer exposed through said openingand formed around an inner wall of said second conductive layer definingsaid opening, said conductive sidewall having a width substantiallyequal to that of said contact hole; and a third conductive layer formedon said second conductive layer, said conductive sidewall and said firstconductive layer exposed through said contact hole, wherein said thirdconductive layer comprises a material which causes no reaction with saidsecond conductive layer and said conductive sidewall.
 24. A layerstructure as claimed in claim 23, wherein: said third conductive layercomprises tungsten; said second conductive layer comprises polysilicon;and said conductive sidewall comprises polysilicon.
 25. A dynamic randomaccess memory comprising: a semiconductor substrate having a firstdiffusion region and a second diffusion region of a transfer transistor;a first insulating layer having a first contact hole exposing said firstdiffusion region, and a second contact hole exposing said seconddiffusion region; a word line covered by said first insulating layer; astacked capacitor which is in contact with said first diffusion regionthrough said first contact hole; a bit line which is in contact withsaid second diffusion region through said second contact hole; and asecond insulating layer covering said stacked capacitor, wherein: saidstacked capacitor comprises a storage electrode, a dielectric film and acell plate; said storage electrode which is in contact with said firstdiffusion region through said first contact hole has a first fin havinga first portion, a second portion and a third portion; said firstportion has a first opening having a width greater than that of saidfirst contact hole; said second portion serving as a sidewall is formedaround an inner wall of said first portion defining said first opening,so that a second opening has a width substantially identical to that ofsaid first contact hole; and said third portion extends on said firstand second portions, substantially vertically extends in said firstcontact hole, and is in contact with said first diffusion region.
 26. Adynamic random access memory as claimed in claim 25, wherein: saidstorage electrode comprises a second fin having a contact area in whichsaid second fin is in contact with said first fin; said contact area iswider than said first contact hole; and said first and second fins arespaced apart from each other.
 27. A dynamic random access memory asclaimed in claim 25, wherein said first fin is spaced apart from saidfirst insulating layer.
 28. A dynamic random access memory as claimed inclaim 25, wherein said first fin of said storage electrode is formed onsaid first insulating layer.
 29. A dynamic random access memory asclaimed in claim 26, wherein said first fin of said storage electrode isthicker than said third portion thereof.
 30. A dynamic random accessmemory as claimed in claim 25, wherein said storage electrode havingsaid first fin having said first, second and third portions comprisespolysilicon.
 31. A dynamic random access memory comprising: asemiconductor substrate having a first diffusion region and a seconddiffusion region of a transfer transistor; a first insulating layerhaving a first contact hole exposing said first diffusion region, and asecond contact hole exposing said second diffusion region; a word linecovered by said first insulating layer; a stacked capacitor which is incontact with said first diffusion region through said first contacthole; a bit line which is in contact with said second diffusion regionthrough said second contact hole; and a second insulating layer coveringsaid stacked capacitor, wherein: said stacked capacitor comprises astorage electrode, a dielectric film and a cell plate; and said storageelectrode which is in contact with said first diffusion region throughsaid first contact hole has a plurality of first fin-shaped portionslocated outside of said first contact hole, a second portion connectingsaid first fin-shaped portions to each other, and a third portionextending on an uppermost one of said first fin-shaped portions and saidsecond portion, substantially vertically extending in said first contacthole, and being in contact with said first diffusion region.
 32. Adynamic random access memory as claimed in claim 31, wherein: saidsecond portion of said storage electrode is spaced apart from said firstinsulating layer; and a lowermost one of said first fin-shaped portionsof said storage electrode is spaced apart from said first insulatinglayer.
 33. A dynamic random access memory as claimed in claim 31,wherein: said second portion of said storage electrode is in contactwith said first insulating layer; and a lowermost one of said firstfin-shaped portions of said storage electrode is spaced apart from saidfirst insulating layer.
 34. A dynamic random access memory as claimed inclaim 33, wherein said storage electrode has a substantially flatsurface which extends above said word line.
 35. A dynamic random accessmemory as claimed in claim 31, wherein said storage electrode comprisespolysilicon.
 36. A dynamic random access memory comprising: asemiconductor substrate having a first diffusion region and a seconddiffusion region of a transfer transistor; a first insulating layerhaving a first contact hole exposing said first diffusion region, and asecond contact hole exposing said second diffusion region; a word linecovered by said first insulating layer; a stacked capacitor which is incontact with said first diffusion region through said first contacthole; a bit line which is in contact with said second diffusion regionthrough said second contact hole; and a second insulating layer coveringsaid stacked capacitor, wherein: said stacked capacitor comprises astorage electrode, a dielectric film and a cell plate; and said storageelectrode which is in contact with said first diffusion region throughsaid first contact hole has a plurality of first fin-shaped portionslocated outside of said first contact hole, and a second portionconnecting said first fin-shaped portions to each other, and extendingon an uppermost one of said first fin-shaped portions, said secondportion substantially vertically extending in said first contact hole,and being in contact with said first diffusion region.
 37. A dynamicrandom access memory as claimed in claim 36, wherein a lowermost one ofsaid first fin-shaped portions is spaced apart from said firstinsulating layer.
 38. A dynamic random access memory device as claimedin claim 36, wherein a lowermost one of said first fin-shaped portionsis in contact with said first insulating layer.
 39. A dynamic randomaccess memory as claimed in claim 36, wherein said storage electrodecomprises polysilicon.
 40. A fin-shaped capacitor comprising: a storageelectrode having an exposed surface; a dielectric film formed aroundsaid exposed surface of said storage electrode; and a cell platecovering said storage electrode surrounded by said dielectric film,wherein: said storage electrode is in contact with a diffusion region ofa semiconductor substrate through a contact hole formed in an insulatinglayer formed on said semiconductor substrate; said storage electrode hasa first fin having a first portion, a second portion and a thirdportion; said first portion has a first opening having a width greaterthan that of said contact hole; said second portion is formed around aninner wall of said first portion defining said first opening, so that asecond opening has a width substantially identical to that of saidcontact hole; and said third portion extends on said first and secondportions, substantially vertically extends in said contact hole, and isin contact with said diffusion region in said semiconductor substrate.41. A fin-shaped capacitor as claimed in claim 40, wherein: said storageelectrode comprises a second fin having a contact area in which saidsecond fin is in contact with said first fin; said contact area is widerthan said contact hole; and said first and second fins are spaced apartfrom each other.
 42. A fin-shaped capacitor as claimed in claim 40,wherein said first fin is spaced apart from said insulating layer.
 43. Afin-shaped capacitor as claimed in claim 40, wherein said first fin ofsaid storage electrode is formed on said insulating layer.
 44. Afin-shaped capacitor as claimed in claim 41, wherein said first fin ofsaid storage electrode is thicker than said third portion thereof.
 45. Afin-shaped capacitor as claimed in claim 40, wherein said storageelectrode having said first fin having said first, second and thirdportions comprises polysilicon.
 46. A fin-shaped capacitor comprising: astorage electrode having an exposed surface; a dielectric film formedaround said exposed surface of said storage electrode; and a cell platecovering said storage electrode surrounded by said storage electrde,wherein: said storage electrode is in contact with a diffusion region ofa semiconductor substrate through a contact hole formed in an insulatinglayer formed on said semiconductor substrate; said storage electrode hasa plurality of first fin-shaped portions located outside of said contacthole, a second portion connecting said first fin-shaped portions to eachother, and a third portion extending on an uppermost one of said firstfin-shaped portions and said second portion, substantially verticallyextending in said contact hole, and being in contact with said diffusionregion of said semiconductor substrate.
 47. A fin-shaped capacitor asclaimed in claim 46, wherein: said second portion of said storageelectrode is spaced apart from said insulating layer; and a lowermostone of said first fin-shaped portions of said storage electrode isspaced apart from said insulating layer.
 48. A fin-shaped capacitor asclaimed in claim 46, wherein: said second portion of said storageelectrode is in contact with said insulating layer; and a lowermost oneof said first fin-shaped portions of said storage electrode is spacedapart from said insulating layer.
 49. A fin-shaped capacitor as claimedin claim 48, wherein said insulating layer has a substantially flatsurface on which said second portion of said storage electrode isformed.
 50. A fin-shaped capacitor as claimed in claim 46, wherein saidstorage electrode comprises polysilicon.
 51. A fin-shaped capacitorcomprising: a storage electrode having an exposed surface; a dielectricfilm formed around said exposed surface of said storage electrode; and acell plate covering said storage electrode surrounded by said storageelectrode, wherein: said storage electrode is in contact with adiffusion region of a semiconductor substrate through a contact holeformed in an insulating layer formed on said semiconductor substrate;said storage electrode has a plurality of first fin-shaped portionslocated outside of said contact hole, and a second portion connectingsaid fin-shaped portions to each other, and extending on an uppermostone of said first fin-shaped portions, said second portion substantiallyvertically extending in said contact hole, and being in contact withsaid diffusion region in said semiconductor substrate.
 52. A fin-shapedcapacitor as claimed in claim 51, wherein a lowermost one of said firstfin-shaped portions is spaced apart from said insulating layer.
 53. Afin-shaped capacitor device as claimed in claim 51, wherein a lowermostone of said first fin-shaped portions is in contact with said insulatinglayer.
 54. A fin-shaped capacitor as claimed in claim 51, wherein saidstorage electrode comprises polysilicon.
 55. A method of producing afin-shaped capacitor in a dynamic random access memory comprising thesteps of: (a) forming an insulating layer on a semiconductor substratehaving a diffusion region; (b) forming a first conductive layer having afirst opening on said insulating layer; (c) forming a conductivesidewall around an inner wall of said first conductive layer definingsaid first opening, said conductive sidewall defining a second openinghaving a width smaller than that of said first opening; (d) selectivelyetching said insulating layer in a state where said first conductivelayer and said conductive sidewall function as etching masks, so thatsaid diffusion region is exposed through a contact hole formed in saidinsulating layer and having a width substantially identical to that ofsaid second opening; (e) forming a second conductive layer on said firstconductive layer, said conductive sidewall and said diffusion regionexposed through said contact hole; (f) patterning said first conductivelayer and said second conductive layer into a shape of a storageelectrode of said fin-shaped capacitor; (g) forming a dielectric filmaround an exposed surface of said storage electrode; and (h) forming acell plate around said storage electrode covered by said dielectricfilm.
 56. A method as claimed in claim 55, wherein said step (a)comprises the steps of: forming a first insulating layer directly onsaid semiconductor substrate; and forming a second insulating layer onsaid semiconductor substrate, said insulating layer having said firstand second insulating layers, and wherein said method further comprisesthe step of isotropically etching said second insulating layer, so thatsaid storage electrode is spaced apart from said first insulating layer.57. A method of producing a fin-shaped capacitor in a dynamic randomaccess memory comprising the steps of: (a) forming a first insulatinglayer on a semiconductor substrate having a diffusion region; (b)forming a first conductive layer having a first opening on said firstinsulating layer; (c) forming a conductive sidewall around an inner wallof said first conductive layer defining said first opening, saidconductive sidewall defining a second opening having a width smallerthan that of said first opening; (d) selectively etching said firstinsulating layer in a state where said first conductive layer and saidconductive sidewall function as etching masks, so that said diffusionregion is exposed through a contact hole formed in said first insulatinglayer and having a width substantially identical to that of said secondopening; (e) forming a second conductive layer on said first conductivelayer, said conductive sidewall and said diffusion region exposedthrough said contact hole; (f) forming, on said second conductive layer,a second insulating layer having a third opening having a widthsubstantially identical to that of said first opening; (g) forming athird conductive layer on said second insulating layer and said secondconductive layer through said third opening; (h) patterning said firstand second conductive layers and said second insulating layer into ashape of a storage electrode of said fin-shaped capacitor; (i)isotropically etching said second insulating layer so as to be removed;(j) forming a dielectric film around an exposed surface of said storageelectrode; and (k) forming a cell plate around said storage electrodecovered by said dielectric film.
 58. A method as claimed in claim 57,wherein said step (a) comprises the steps of: forming a third insulatinglayer directly on said semiconductor substrate; and forming a fourthinsulating layer on said third insulating layer; forming a fifthinsulating layer on said fourth insulating layer, said first insulatinglayer has said third and fourth insulating layers, and wherein: saidfifth insulating layer is formed of a material identical to that of saidthird insulating material; and said fifth insulating layer is removedduring said step (i), so that said storage electrode is spaced apartfrom said fourth insulating layer.
 59. A method as claimed in claim 57,wherein: said step (h) comprises: forming a third insulating layerhaving a fourth opening on said third conductive layer, said fourthopening being located at a position different from that of said firstopening; forming an insulating sidewall around an inner surface of saidfourth insulating layer defining said fourth opening, said insulatingsidewall defining a fifth opening having a width smaller than that ofsaid fourth opening; and etching said first, second and third conductivelayers and said second and third insulating layers in a state where saidfourth insulating layer and said insulating sidewall function as etchingmasks.
 60. A method of producing a fin-shaped capacitor in a dynamicrandom access memory comprising the steps of: (a) forming a firstinsulating layer on a semiconductor substrate having a diffusion region;(b) forming a plurality of stacked-layer structures, a lowermost one ofsaid stacked-layer structures being formed on said first insulatinglayer, each of said stacked-layer structures having a spacer layer and afirst conductive layer; (c) forming a first opening in saidstacked-layer structures except said spacer layer of said lowermost oneof said stacked-layer structures; (d) forming a conductive sidewallaround an inner wall of said stacked-layer structures defining saidfirst opening, said conductive sidewall defining a second opening havinga width smaller than that of said first opening; (e) selectively etchingsaid spacer layer of the lowermost one of said stacked-layer structuresand said first insulating layer in a state where said first conductivelayer of an uppermost one of said stacked layer structures and saidconductive sidewall function as masks, so that said diffusion region isexposed through a contact hole formed in said spacer layer of thelowermost one of said stacked-layer structures and said first insulatinglayer; (f) forming a second conductive layer on said first conductivelayer of the uppermost one of said stacked-layer structures, saidconductive sidewall and said diffusion region exposed through saidcontact hole; (g) patterning said second conductive layer and saidstacked-layer structures except said spacer layer of the lowermost oneof said stacked-layer structures into a shape of a storage electrode ofsaid fin-shaped capacitor; (h) isotropically etching said spacer layerof each of said stacked-layer structures so that said spacer layer isremoved; (i) forming a dielectric film around said storage electrode;and (j) forming a cell plate around said storage electrode covered bysaid dielectric film.
 61. A method as claimed in claim 60, wherein: saidmethod further comprises, between said steps (b) and (c), the step offorming a second insulating layer on said first conductive layer of theuppermost one of said stacked-layer structures; and said secondinsulating layer is removed during said step (e).
 62. A method asclaimed in claim 60, wherein said step (a) comprises the steps of:forming a second insulating layer on said semiconductor substrate;forming a third insulating layer on said second insulating layer;heating said third insulating layer so that said third insulating layerhas a substantially flat surface; and forming a fourth insulating layeron said substantially flat surface of said third insulating layer, andwherein: said second, third and fourth insulating layers form said firstinsulating layer.
 63. A method as claimed in claim 60, wherein: saidfirst conductive layer comprises polysilicon; and said spacer layercomprises silicon oxide.
 64. A method as claimed in claim 62, wherein:said second and fourth insulating layers comprises silicon oxide; andsaid third insulating layer comprises one of a spin-on-glass layer and aphosphosilicate glass layer.
 65. A method of producing a fin-shapedcapacitor in a dynamic random access memory comprising the steps of: (a)forming a first insulating layer on a semiconductor substrate having adiffusion region; (b) forming a plurality of stacked-layer structures, alowermost one of said stacked-layer structures being formed on saidfirst insulating layer, each of said stacked-layer structures having aspacer layer and a first conductive layer; (c) forming a first openingin said stacked-layer structures; (d) forming a conductive sidewallaround an inner wall of said stacked-layer structures defining saidfirst opening, said conductive sidewall defining a second opening havinga width smaller than that of said first opening; (e) selectively etchingsaid first insulating layer in a state where said first conductive layerof an uppermost one of said stacked layer structures and said conductivesidewall function as masks, so that said diffusion region is exposedthrough a contact hole formed in said first insulating layer; (f)forming a second conductive layer on said first conductive layer of theuppermost one of said stacked-layer structures, said conductive sidewalland said diffusion region exposed through said contact hole; (g)patterning said second conductive layer and said stacked-layerstructures into a shape of a storage electrode of said fin-shapedcapacitor; (h) isotropically etching said spacer layer of each of saidstacked-layer structures so that said spacer layer is removed; (i)forming a dielectric film around said storage electrode; and (j) forminga cell plate around said storage electrode covered by said dielectricfilm.
 66. A method as claimed in claim 65, wherein: said method furthercomprises, between said steps (b) and (c), the step of forming a secondinsulating layer on said first conductive layer of the uppermost one ofsaid stacked-layer structures; and said second insulating layer isremoved during said step (e).
 67. A method as claimed in claim 65,wherein said step (a) comprises the steps of: forming a secondinsulating layer on said semiconductor substrate; forming a thirdinsulating layer on said second insulating layer; heating said thirdinsulating layer so that said third insulating layer has a substantiallyflat surface; and forming a fourth insulating layer on saidsubstantially flat surface of said third insulating layer, and wherein:said second, third and fourth insulating layers form said firstinsulating layer.
 68. A method as claimed in claim 65, wherein: saidfirst conductive layer comprises polysilicon; and said spacer layercomprises silicon oxide.
 69. A method as claimed in claim 67, wherein:said second and fourth insulating layers comprise silicon oxide; andsaid third insulating layer comprises one of a spin-on-glass layer and aphosphosilicate glass layer.
 70. A method of producing a fin-shapedcapacitor in a dynamic random access memory comprising the steps of: (a)forming a first insulating layer on a semiconductor substrate having adiffusion region; (b) forming a plurality of stacked-layer structures, alowermost one of said stacked-layer structures being formed on saidfirst insulating layer, each of said stacked-layer structures having aspacer layer and a first conductive layer; (c) forming a contact hole insaid stacked-layer structures and said first insulating layer so thatsaid diffusion layer is exposed through said contact hole; (d) forming asecond conductive layer on said first conductive layer of an uppermostone of said stacked-layer structure and said diffusion layer exposedthrough said contact hole, said second conductive layer substantiallyvertically extending along an inner wall of said contact hole; (e)patterning said second conductive layer and said stacked-layerstructures into a shape of a storage electrode of said fin-shapedcapacitor; (f) isotropically etching said spacer layer of each of saidstacked-layer structures so that said spacer layer is removed; (i)forming a dielectric film around said storage electrode; and (j) forminga cell plate around said storage electrode covered by said dielectricfilm.
 71. A method as claimed in claim 70, wherein said step (a)comprises the steps of: forming a second insulating layer on saidsemiconductor substrate; forming a third insulating layer on said secondinsulating layer; heating said third insulating layer so that said thirdinsulating layer has a substantially flat surface; and forming a fourthinsulating layer on said substantially flat surface of said thirdinsulating layer, and wherein: said fourth insulating layer is removedduring said step (f).
 72. A method as claimed in claim 71, wherein: saidsecond and fourth insulating layers comprises silicon oxide; said thirdinsulating layer comprises silicon nitride; and said first and secondconductive layers comprise polysilicon.
 73. A method as claimed in claim70, wherein: said step (c) comprises: forming a third conductive layeron a top of said stacked layer structures; forming a second insulatinglayer on said third conductive layer; forming a photoresist film havinga window pattern on said second insulating layer; etching said secondinsulating layer and said third conductive layer so that a first windowis formed in said third conductive layer and said second insulatinglayer; removing said photoresist film; and forming a conductive sidwallaround an inner wall of said third conductor layer defining said window,wherein said contact hole formed by said step (c) having a size definedby said conductive sidewall.